{"id":349,"date":"2018-06-19T21:51:40","date_gmt":"2018-06-19T18:51:40","guid":{"rendered":"http:\/\/www.scozturk.com\/?p=349"},"modified":"2025-08-29T10:44:53","modified_gmt":"2025-08-29T10:44:53","slug":"verilog-sayisal-tasarim-onerileri-i","status":"publish","type":"post","link":"http:\/\/18.193.70.38\/?p=349&lang=tr","title":{"rendered":"Verilog Say\u0131sal Tasar\u0131m \u00d6nerileri – I – Sentezlenebilirlik ve Temel \u00d6neriler"},"content":{"rendered":"

#1: if varsa else de olmal\u0131d\u0131r<\/strong><\/em>
\nVerilog ile say\u0131sal tasar\u0131m tarifi yaparken, if blo\u011fu koydu\u011funuzda else blo\u011fu koyman\u0131z faydal\u0131d\u0131r. Bu sayede if blo\u011funda tan\u0131mlad\u0131\u011f\u0131n\u0131z durumlar d\u0131\u015f\u0131nda da ne bekledi\u011finizi net bir bi\u00e7imde sentezleme arac\u0131na belirtmi\u015f olursunuz, sizin a\u00e7\u0131n\u0131zdan da durum net olur.<\/p>\n

\u015eu \u015fekilde tan\u0131m yapmak yerine:<\/p>\n

\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r <= 8'h00;\n\tend\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10) begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\tend\nend\n<\/pre>\n
\u015e\u00f6yle bir tan\u0131m yapmak daha yerinde olacakt\u0131r:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r <= 8'h00;\n\tend\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10) begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\tend\nend\n<\/pre>\n
Bu sayede in_sinyal<\/em> i\u00e7in 2’b11<\/em> ve 2’b00<\/em> durumlar\u0131nda yazmacim_r<\/em> yazmac\u0131n\u0131n de\u011ferinin korunmas\u0131 gerekti\u011fini de a\u00e7\u0131k olarak belirttik. Bariz noktalar i\u00e7in fazlaca kod yaz\u0131lm\u0131\u015f gibi gelebilir, fakat s\u00fcrprizlerle kar\u015f\u0131la\u015fma ihtimali azalacakt\u0131r. Belki de yukar\u0131daki \u00f6rnekte 2’b11<\/em> durumunda yazmacim_r<\/em> yazmac\u0131n\u0131 kendisine e\u015fitlemek istemiyordunuz, ama unuttunuz, bu ifade \u015fekli bu durumlar\u0131 daha net kar\u015f\u0131n\u0131za \u00e7\u0131karmaktad\u0131r.<\/p>\n
#2: if\/else bloklar\u0131 tek sat\u0131r da olsa begin\/end i\u00e7erisinde gruplanmal\u0131d\u0131r<\/strong><\/em>
\n\u0130\u00e7erisinde tek sat\u0131r ifadeleriniz olsa bile if<\/em> ve else<\/em> bloklar\u0131n\u0131z\u0131n \u00e7evresini begin\/end<\/em> ile sarman\u0131z ileride hata yapman\u0131z\u0131 \u00f6nleyecektir. Benzer \u015fekilde tasar\u0131m\u0131n\u0131z\u0131 daha okunakl\u0131 hale getirerek bak\u0131m\u0131n\u0131 da kolayla\u015ft\u0131racakt\u0131r.<\/p>\n
\u015eu kodu inceleyelim:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\t\tyazmacim2_r <= 32'h07070707;\n        end\n\telse begin\n\t\tif(in_sinyal == 2'b01) \n\t\t\tyazmacim_r <= 8'h06;\n\t\telse if(in_sinyal == 2'b10) \n\t\t\tyazmacim_r <= 8'h42;\n\t\telse \n\t\t\tyazmacim_r <= yazmacim_r;\n\t\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
yazmacim2_r<\/em> yazmac\u0131n\u0131n tam ne oldu\u011fu belli de\u011fil gibi de\u011fil mi? Bir de \u015fu koda bakal\u0131m:<\/p>\n
\nalways @ (posedge in_clock) begin\nif(!in_reset) begin\nyazmacim_r \t<= 8'h00;\nyazmacim2_r <= 32'h07070707;\nend\nelse begin\nif(in_sinyal == 2'b01) \nyazmacim_r <= 8'h06;\nelse if(in_sinyal == 2'b10) \nyazmacim_r <= 8'h42;\nelse \nyazmacim_r <= yazmacim_r;\nyazmacim2_r <= yazmacim2_r;\nend\nend\n<\/pre>\n
Her \u015fey ayn\u0131, sadece sat\u0131r aral\u0131klar\u0131 kald\u0131r\u0131ld\u0131, \u00e7ok daha kar\u0131\u015f\u0131k. Bunun yerine \u015fu yaz\u0131m tarz\u0131 her \u015feyi daha net yapacakt\u0131r:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\t\tyazmacim2_r <= 32'h07070707;\n        end\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
Bu tarz basit tasar\u0131mlarda \u00e7ok da \u00f6nemli gelmeyebilir, fakat daha kapsaml\u0131 tasar\u0131mlarda anla\u015f\u0131labilirli\u011fi artt\u0131racakt\u0131r. Bu \u00f6rnek asl\u0131nda kendi i\u00e7erisinde yazmacim2_r<\/em> yazmac\u0131n\u0131n tan\u0131m\u0131 nedeniyle sorunlu (bir sonraki maddede bu sorunu ele al\u0131yoruz), fakat maddenin amac\u0131n\u0131 g\u00fczel anlat\u0131yor.<\/p>\n
#3: \u0130\u00e7 i\u00e7e if\/else bloklar\u0131nda de\u011fer atamalar\u0131 yap\u0131l\u0131yorsa, m\u00fcmk\u00fcnse her bir if\/else i\u00e7erisinde net olarak de\u011fer atamas\u0131 durumu belirtilmelidir<\/strong><\/em>
\nBir \u00fcstteki \u00f6rne\u011fi tekrar ele alal\u0131m:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\t\tyazmacim2_r <= 32'h07070707;\n        end\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
Bu kod blo\u011fu ile yazmacim2_r<\/em> yazmac\u0131n\u0131n asl\u0131nda her durumda kendisine e\u015fit oldu\u011funu bildiriyoruz, yani bir bak\u0131ma statik bir ROM de\u011feri tan\u0131ml\u0131yoruz. Peki bu durumda yazmacim2_r<\/em> yazmac\u0131 in_sinyal<\/em> girdisinden ba\u011f\u0131ms\u0131z bir yazma\u00e7 de\u011fil midir? Neden birbirinden ba\u011f\u0131ms\u0131z sinyalleri sanal olarak ayn\u0131 kod blo\u011funda tan\u0131mlayarak anla\u015f\u0131labilirli\u011fi \u00f6ld\u00fcr\u00fcyoruz? Bunun yerine \u015fu yaz\u0131m tarz\u0131n\u0131 tercih etsek her \u015fey daha anla\u015f\u0131l\u0131r olacakt\u0131r:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n        end\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\tend\nend\n\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim2_r <= 32'h07070707;\n        end\n\telse begin\n\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
Bu \u015fekilde herkes rahatl\u0131kla yazmacim2_r<\/em> yazmac\u0131n\u0131n in_sinyal<\/em> ve yazmacim_r<\/em>‘dan ba\u011f\u0131ms\u0131z oldu\u011funu g\u00f6rebiliyor.<\/p>\n
Ba\u015fka bir a\u00e7\u0131dan sorunu ele alabilmek i\u00e7in \u015fu durumu ele alal\u0131m:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\t\tyazmacim2_r <= 32'h07070707;\n\tend\n\telse if(in_sinyal2 == 2'b01) begin\n\t\tyazmacim_r \t<= yazmacim_r + 1;\n\t\tyazmacim2_r <= 32'hFB070707;\n\tend\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
Bu \u00f6rnekte yazmacim_r<\/em> ile yazmacim2_r<\/em>‘\u0131 bir bak\u0131m\u0131 ayn\u0131 blokta ele almay\u0131 bir nebze ge\u00e7erli k\u0131lmaya \u00e7al\u0131\u015ft\u0131k. Burada da anla\u015f\u0131labilirli\u011fi zorla\u015ft\u0131rm\u0131\u015f olduk, bunun yerine \u015fu yaz\u0131m \u015fekli daha do\u011fru olacakt\u0131r:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\t\tyazmacim2_r <= 32'h07070707;\n\tend\n\telse if(in_sinyal == 2'b00) begin\n\t\tyazmacim_r \t<= yazmacim_r + 1;\n\t\tyazmacim2_r <= 32'hFB070707;\n\tend\n\telse begin\n\t\tif(in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\t\tyazmacim2_r <= yazmacim2_r;\n\t\tend\n\t\telse if(in_sinyal == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\t\tyazmacim2_r <= yazmacim2_r;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\t\tyazmacim2_r <= yazmacim2_r;\n\t\tend\n\tend\nend\n<\/pre>\n
Fakat “hay\u0131r, ben yazmacim2_r<\/em>‘\u0131 in_sinyal<\/em>‘den ba\u011f\u0131ms\u0131z olarak tan\u0131mlamak istiyorum, b\u00f6yle neden yazay\u0131m, sa\u00e7ma!” diyorsan\u0131z, do\u011frusu \u015fu olurdu:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\tend\n\telse begin\n\t\tif(in_sinyal == 2'b00) begin\n\t\t\tyazmacim_r <= yazmacim_r + 1;\n\t\tend\n\t\telse (in_sinyal == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(in_sinyal == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\tend\nend\n\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim2_r <= 32'h07070707;\n\tend\n\telse if(in_sinyal == 2'b00) begin\n\t\tyazmacim2_r <= 32'hFB070707;\n\tend\n\telse begin\n\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
Hatta b\u00f6yle bir niyetiniz varsa sentez arac\u0131n\u0131n bu 2 kod blo\u011funun tarif etti\u011fi elektronik devreyi daha rahat optimize etmesini sa\u011flamak i\u00e7in \u015f\u00f6yle bir iyile\u015ftirme de yapabilirsiniz:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tsinyal_buffer_1_r \t<= 1'b0;\n\tend\n\telse begin\n\t\tsinyal_buffer_1_r <= in_sinyal;\n\tend\nend\n\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tsinyal_buffer_2_r \t<= 1'b0;\n\tend\n\telse begin\n\t\tsinyal_buffer_2_r <= in_sinyal;\n\tend\nend\n\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_r \t<= 8'h00;\n\tend\n\telse begin\n\t\tif(sinyal_buffer_1_r == 2'b00) begin\n\t\t\tyazmacim_r <= yazmacim_r + 1;\n\t\tend\n\t\telse (sinyal_buffer_1_r == 2'b01) begin\n\t\t\tyazmacim_r <= 8'h06;\n\t\tend\n\t\telse if(sinyal_buffer_1_r == 2'b10)  begin\n\t\t\tyazmacim_r <= 8'h42;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_r <= yazmacim_r;\n\t\tend\n\tend\nend\n\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim2_r <= 32'h07070707;\n\tend\n\telse if(sinyal_buffer_2_r == 2'b00) begin\n\t\tyazmacim2_r <= 32'hFB070707;\n\tend\n\telse begin\n\t\tyazmacim2_r <= yazmacim2_r;\n\tend\nend\n<\/pre>\n
Kontrol giri\u015flerini iki ayr\u0131 bufferla bufferlayarak devre bloklar\u0131n\u0131n birbirinden daha uzaklara konabilmesini sa\u011flayabilirsiniz, zamanlamalar daha rahat tutturulacakt\u0131r.<\/p>\n
#4: if\/else bloklar\u0131ndan birinde bir yazma\u00e7\/registera bir de\u011fer atand\u0131ysa, di\u011ferlerinde de bir de\u011fer atanmal\u0131d\u0131r<\/strong><\/em>
\nBu sayede her durumu de\u011ferlendirdi\u011finiz net bir bi\u00e7imde ortaya \u00e7\u0131kacak, genel kural olarak uygulad\u0131\u011f\u0131n\u0131zda herhangi bir durumu unutmad\u0131\u011f\u0131n\u0131z belli olacak ve sentezleme arac\u0131n\u0131n tam olarak istedi\u011finiz \u015fekilde sentezlemesini sa\u011flayabileceksiniz. \u00d6rnekleyelim:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_1_r \t<= 8'h00;\n\t\tyazmacim_3_r \t<= 8'h00;\n\tend\n\telse begin\n\t\tif(fsm_control_r == 3'b000) begin\n\t\t\tyazmacim_1_r \t<= yazmacim_1_r + 1;\n\t\t\tyazmacim_3_r \t<= 8'h42;\n\t\t\tyazmacim_2_r \t<= 8'h06;\n\t\tend\n\t\telse (fsm_control_r == 3'b001) begin\n\t\t\tyazmacim_1_r \t<= 8'h06;\n\t\t\tyazmacim_2_r \t<= 8'h08;\n\t\tend\n\t\telse if(fsm_control_r == 3'b010)  begin\n\t\t\tyazmacim_1_r \t<= 8'h42;\n\t\t\tyazmacim_3_r \t<= 8'h02;\n\t\tend\n\t\telse if(fsm_control_r == 3'b100)  begin\n\t\t\tyazmacim_1_r \t<= 8'h42;\n\t\t\tyazmacim_3_r \t<= 8'h03;\n\t\t\tyazmacim_2_r \t<= 8'h05;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_1_r \t<= yazmacim_1_r;\n\t\t\tyazmacim_3_r \t<= 8'h00;\n\t\tend\n\tend\nend\n<\/pre>\n
Tasar\u0131m\u0131 yerine a\u015fa\u011f\u0131daki tasar\u0131m daha anla\u015f\u0131labilir olacakt\u0131r:<\/p>\n
\nalways @ (posedge in_clock) begin\n\tif(!in_reset) begin\n\t\tyazmacim_1_r \t<= 8'h00;\n\t\tyazmacim_2_r \t<= 8'h55;\n\t\tyazmacim_3_r \t<= 8'h00;\n\tend\n\telse begin\n\t\tif(fsm_control_r == 3'b000) begin\n\t\t\tyazmacim_1_r \t<= yazmacim_1_r + 1;\n\t\t\tyazmacim_2_r \t<= 8'h06;\n\t\t\tyazmacim_3_r \t<= 8'h42;\n\t\tend\n\t\telse (fsm_control_r == 3'b001) begin\n\t\t\tyazmacim_1_r \t<= 8'h06;\n\t\t\tyazmacim_2_r \t<= 8'h08;\n\t\t\tyazmacim_3_r \t<= yazmacim_3_r;\n\t\tend\n\t\telse if(fsm_control_r == 3'b010)  begin\n\t\t\tyazmacim_1_r \t<= 8'h42;\n\t\t\tyazmacim_2_r \t<= yazmacim_2_r;\n\t\t\tyazmacim_3_r \t<= 8'h02;\n\t\tend\n\t\telse if(fsm_control_r == 3'b100)  begin\n\t\t\tyazmacim_1_r \t<= 8'h42;\n\t\t\tyazmacim_2_r \t<= 8'h05;\n\t\t\tyazmacim_3_r \t<= 8'h03;\n\t\tend\n\t\telse begin\n\t\t\tyazmacim_1_r \t<= yazmacim_1_r;\n\t\t\tyazmacim_2_r \t<= yazmacim_2_r;\n\t\t\tyazmacim_3_r \t<= 8'h00;\n\t\tend\n\tend\nend\n<\/pre>\n
Her durumda neyin ne olmas\u0131 gerekti\u011fi a\u00e7\u0131k\u00e7a ortada.<\/p>\n
Umar\u0131m \u00f6neriler i\u015finize yarar, iyi tasar\u0131mlar.<\/p>\n","protected":false},"excerpt":{"rendered":"
#1: if varsa else de olmal\u0131d\u0131r Verilog ile say\u0131sal tasar\u0131m tarifi yaparken, if blo\u011fu koydu\u011funuzda else blo\u011fu koyman\u0131z faydal\u0131d\u0131r. Bu sayede if blo\u011funda tan\u0131mlad\u0131\u011f\u0131n\u0131z durumlar d\u0131\u015f\u0131nda da ne…<\/p>\n","protected":false},"author":1,"featured_media":350,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[207,191,209],"tags":[211,261,251,213,263,255,217,257,259],"class_list":["post-349","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-donanim-tr","category-teknik-tr","category-verilog-tr","tag-fpga-tr","tag-if-tr","tag-if-else-tr","tag-oneriler-tr","tag-register-tr","tag-sayisal-tr","tag-verilog-tr","tag-vhdl-tr","tag-yazmac-tr"],"_links":{"self":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/349","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=349"}],"version-history":[{"count":1,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/349\/revisions"}],"predecessor-version":[{"id":1206,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/349\/revisions\/1206"}],"wp:featuredmedia":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/media\/350"}],"wp:attachment":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=349"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=349"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=349"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}