{"id":355,"date":"2018-06-23T17:54:53","date_gmt":"2018-06-23T14:54:53","guid":{"rendered":"http:\/\/www.scozturk.com\/?p=355"},"modified":"2025-08-29T07:26:59","modified_gmt":"2025-08-29T07:26:59","slug":"verilog-sayisal-tasarim-onerileri-ii","status":"publish","type":"post","link":"http:\/\/18.193.70.38\/?p=355&lang=tr","title":{"rendered":"Verilog Say\u0131sal Tasar\u0131m \u00d6nerileri &#8211; II &#8211; Sentezlenebilirlik ve Temel \u00d6neriler"},"content":{"rendered":"<p><em><strong>#5: Mod\u00fcllerde port isimlendirmeleri m\u00fcmk\u00fcnse standart olmal\u0131 ve m\u00fcmk\u00fcn mertebe a\u00e7\u0131klay\u0131c\u0131 olmal\u0131d\u0131r<\/strong><\/em><br \/>\nKapsaml\u0131 bir say\u0131sal devre tasar\u0131m\u0131 yaparken giri\u015f\/\u00e7\u0131k\u0131\u015f kap\u0131lar\u0131 ile ilgili ya\u015fanan temel sorunlar ve zorluklar:<\/p>\n<ul>\n<li>Kap\u0131 bir giri\u015f <em>(input)<\/em> portu yoksa giri\u015f\/\u00e7\u0131k\u0131\u015f <em>(inout)<\/em> portu mu?<\/li>\n<li>Kap\u0131 bir \u00e7\u0131k\u0131\u015f<em> (output)<\/em> portu yoksa giri\u015f\/\u00e7\u0131k\u0131\u015f <em>(inout)<\/em> portu mu?<\/li>\n<li>Bu bir tel (wire) veya yazma\u00e7 (register) olmas\u0131n?<\/li>\n<li>Bu hatta tampon (buffer) uygulam\u0131\u015f m\u0131yd\u0131m?<\/li>\n<li>Bu d\u0131\u015far\u0131dan gelen saat (clock) hatt\u0131 m\u0131yd\u0131?<\/li>\n<li>&#8230;<\/li>\n<\/ul>\n<p>\u015feklinde olabilmektedir. \u00d6rne\u011fin \u015fu tasar\u0131m kesitini inceleyelim:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @ (posedge clock_200MHz) begin\n\tif(!reset) begin\n\t\tveri &lt;=  8'h00;\n\tend\n\telse begin\n\t\tveri &lt;=  sinyal1 | sinyal2;\n\tend\nend\n...\n<\/pre>\n<p>Kod olduk\u00e7a a\u00e7\u0131klay\u0131c\u0131 ve basit. Fakat anla\u015f\u0131labilirlik o kadar y\u00fcksek de\u011fil. Bu koda bakt\u0131\u011f\u0131mda beni teredd\u00fcte d\u00fc\u015f\u00fcren a\u015fa\u011f\u0131daki noktalar oluyor:<\/p>\n<ul>\n<li><em>sinyal1<\/em> veya <em>sinyal2<\/em> hatt\u0131 d\u0131\u015far\u0131dan gelen bir <em>input<\/em> hatt\u0131 m\u0131 yoksa <em>inout<\/em> hatt\u0131 m\u0131d\u0131r? <\/li>\n<li>Saat sinyali olan <em>clock_200MHz<\/em> d\u0131\u015far\u0131dan gelen bir saat sinyali mi yoksa tasar\u0131m i\u00e7erisinde ben mi olu\u015fturdum?<\/li>\n<li><em>reset<em> sinyali d\u0131\u015far\u0131dan gelen bir genel (global) ilklendirme sinyali midir?<\/li>\n<\/ul>\n<p>Bu sorular\u0131n cevab\u0131n\u0131 alabilmek i\u00e7in tasar\u0131m\u0131m\u0131n kalan k\u0131sm\u0131na bak\u0131p durumu \u00e7\u00f6zmem gerekiyor. Bunun yerine \u015fu yaz\u0131m stilini tercih etseydim:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @ (posedge in_clock_200MHz) begin\n\tif(!in_reset) begin\n\t\tveri &lt;=  8'h00;\n\tend\n\telse begin\n\t\tveri &lt;=  in_sinyal1 | sinyal2;\n\tend\nend\n...\n<\/pre>\n<p>Yukar\u0131daki tasar\u0131m kesitini inceleyince ise sorular\u0131m\u0131n tamam\u0131n\u0131n cevapland\u0131\u011f\u0131n\u0131 g\u00f6r\u00fcyorum, ek bir dok\u00fcmentasyon yada 800 sat\u0131rl\u0131k tasar\u0131m\u0131m\u0131 ba\u015ftan incelememe gerek yok.<\/p>\n<p>Fakat burada da bir sorun var, in_reset sinyalim sanki ters mant\u0131k (negative logic) \u00e7al\u0131\u015f\u0131yor, \u00f6yle olmayadabilir. \u015eu yaz\u0131m\u0131 tercih etseydim emin olabilirdim:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @ (posedge in_clock_200MHz) begin\n\tif(!in_reset_n) begin\n\t\tveri &lt;=  8'h00;\n\tend\n\telse begin\n\t\tveri &lt;=  in_sinyal1 | sinyal2;\n\tend\nend\n...\n<\/pre>\n<p>Tamamen yaz\u0131m tarz\u0131 m\u0131? Evet. Fonksiyonel bir fark yarat\u0131yor mu? Hay\u0131r. Tasar\u0131m\u0131 yapan ki\u015fi i\u00e7in kolayl\u0131klar sa\u011fl\u0131yor mu? Evet. O zaman buna benzer bir standart kod i\u00e7erisinde bulunmas\u0131 ve genel olarak tasarlad\u0131\u011f\u0131n\u0131z b\u00fct\u00fcn IP core&#8217;larda bulunmas\u0131 tasar\u0131m anla\u015f\u0131labilirli\u011fi ve bak\u0131m\u0131n\u0131 kolayla\u015ft\u0131racak\/ucuzlatacakt\u0131r.<\/p>\n<p>Bunun i\u00e7in benim kulland\u0131\u011f\u0131m y\u00f6ntem genel olarak:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\ninput in_bir_input;\noutput out_bir_output;\ninput inout_yuksek_empedans_hatti;\ninput in_reset_n;\n...\n<\/pre>\n<p>\u015feklindedir. Benzer bir standart tabii ki dilendi\u011fi gibi olu\u015fturulabilir.<\/p>\n<p><em><strong>#6: Register, wire ve parametre isimlendirmeleri m\u00fcmk\u00fcnse standart olmal\u0131 ve m\u00fcmk\u00fcn mertebe a\u00e7\u0131klay\u0131c\u0131 olmal\u0131d\u0131r<\/strong><\/em><br \/>\nBir \u00fcstteki \u00f6neri aynen register, wire ve parametre tan\u0131mlamalar\u0131nda da ge\u00e7erlidir. \u00d6rne\u011fi hafif de\u011fi\u015ftirerek tekrarlayal\u0131m:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @ (posedge in_clock_200MHz) begin\n\tif(!in_reset_n) begin\n\t\tveri &lt;=  8'h00;\n\tend\n\telse begin\n\t\tif(deger1 == deger2) begin\n\t\t\tveri &lt;=  in_sinyal1 | sinyal2;\n\t\tend\n\t\telse begin\n\t\t\tveri &lt;= sinyal3;\n\t\tend\n\tend\nend\n...\n<\/pre>\n<p>B\u00f6yle bir tasar\u0131m g\u00f6rd\u00fc\u011f\u00fcmde akl\u0131mda \u015fu sorular beliriyor:<\/p>\n<ul>\n<li><em>deger1<\/em> bir <em>register<\/em> m\u0131? <em>Wire<\/em> m\u0131?<\/li>\n<li><em>deger2<\/em> bir <em>parameter<\/em> m\u0131 yoksa?<\/li>\n<li><em>sinyal2<\/em> bir <em>wire<\/em> olsa gerek?<\/li>\n<li><em>veri<\/em> umar\u0131m bir <em>register<\/em>d\u0131r?<\/li>\n<li>Ya <em>sinyal3<\/em> de nedir?<\/li>\n<li>&#8230;<\/li>\n<\/ul>\n<p>Bu kod blo\u011funu \u00e7\u00f6zebilmek i\u00e7in b\u00fcy\u00fck ihtimalle tasar\u0131m\u0131n birka\u00e7 noktas\u0131na daha bakmak veya bir \u00e7e\u015fit dok\u00fcmantasyona bakmak gerekiyor. Bunun yerine \u015f\u00f6yle bir stil tercih edilebilir:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @ (posedge in_clock_200MHz) begin\n\tif(!in_reset_n) begin\n\t\tveri_r &lt;=  8'h00;\n\tend\n\telse begin\n\t\tif(deger1_r == deger2_p) begin\n\t\t\tveri_r &lt;=  in_sinyal1 | sinyal2_r;\n\t\tend\n\t\telse begin\n\t\t\tveri_r &lt;= sinyal3_w;\n\t\tend\n\tend\nend\n...\n<\/pre>\n<p>Her \u015fey \u00e7ok daha a\u00e7\u0131k. &#8220;veri_r&#8221; bir yazma\u00e7, <em>sinyal3_w<\/em> bir tel, <em>deger2_p<\/em> ise bir parametre. En az\u0131ndan register\/wire\/parametre sorular\u0131n\u0131n hepsine sadece stile bakarak cevap vermek m\u00fcmk\u00fcn olabiliyor, bu birimlerin fiili olarak ne i\u015fe yarad\u0131\u011f\u0131 ise ayr\u0131 bir konu. \u00d6zetle:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nwire bir_tel_w;\nreg bir_yazmac_r;\nparameter bir_parametre_p;\n...\n<\/pre>\n<p>gibi bir standart yaz\u0131m tarz\u0131 anla\u015f\u0131labilirli\u011fi artt\u0131rmaktad\u0131r.<\/p>\n<p><em><strong>#7: case\/end kullan\u0131m\u0131 yap\u0131l\u0131yorsa bu ayr\u0131 bir always blo\u011funda olmal\u0131d\u0131r<\/strong><\/em><br \/>\nBir <em>always<\/em> blo\u011fu i\u00e7erisinde <em>if\/else<\/em> ve <em>case\/end<\/em> kullan\u0131m\u0131 beraber olmamal\u0131d\u0131r, m\u00fcmk\u00fcnse bu iki blok par\u00e7alanmal\u0131d\u0131r. <\/p>\n<p>Mant\u0131ken, say\u0131sal tasar\u0131m yap\u0131ld\u0131\u011f\u0131ndan, bu iki ifade \u015fekli ile farkl\u0131 yap\u0131lar ve genelde de 2 farkl\u0131 say\u0131sal tasar\u0131m blo\u011fu ifade edilmek istenmektedir. Bu durumda da bunlar\u0131 iki farkl\u0131 <em>always<\/em> blo\u011funa par\u00e7alamak hem anla\u015f\u0131labilirli\u011fi hem de hata ihtimallerini ortadan kald\u0131rmaktad\u0131r. \u015eu \u00f6rne\u011fe bir g\u00f6z atal\u0131m:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @(posedge in_clock) begin\n\tcase (status_r)\n\t\tIDLE :begin  \n\t\t\tclock_count_r &lt;= 0;\n\t\tend\n\t\tRUN : begin\n\t\t\tclock_count_r &lt;= clock_count_r + 1;\n\t\tend \n\t\tdefault:    \n\t\t\tclock_count_r &lt;= clock_count_r;\n\tendcase\n\tif((clock_count_r &lt; 503) &amp;&amp; (reg_in_flow_control==1'b1))begin\n        cts_r &lt;= 1'b1; \n    end\n    else begin\n        cts_r &lt;= 1'b0;\n    end\nend  \n...\n<\/pre>\n<p>Bir always blo\u011funu verimli kullanmak d\u0131\u015f\u0131nda pratikte hi\u00e7bir anlam\u0131 yoktur. Bunun yerine a\u015fa\u011f\u0131daki yaz\u0131m\u0131n tercih edilmesi (\u00f6zellikle case blo\u011funda 2&#8217;den fazla b\u00f6l\u00fcm i\u00e7eren anlaml\u0131 b\u00fcy\u00fck bir tasar\u0131mda) tasar\u0131m\u0131n niyetini daha anla\u015f\u0131labilir k\u0131lacakt\u0131r:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @(posedge in_clock) begin\n\tcase (status_r)\n\t\tIDLE :begin  \n\t\t\tclock_count_r &lt;= 0;\n\t\tend\n\t\tRUN : begin\n\t\t\tclock_count_r &lt;= clock_count_r + 1;\n\t\tend \n\t\tdefault:    \n\t\t\tclock_count_r &lt;= clock_count_r;\n\tendcase\n\nend  \n\nalways @(posedge in_clock) begin\n    if((clock_count_r &lt; 503) &amp;&amp; (reg_in_flow_control==1'b1))begin\n        cts_r &lt;= 1'b1; \n    end\n    else begin\n        cts_r &lt;= 1'b0;\n    end\nend \n...\n<\/pre>\n<p>\u00c7ok basit bir ayr\u0131m yaparak anla\u015f\u0131labilirli\u011fi olduk\u00e7a y\u00fcksek derecede artt\u0131rabildik. \u0130lk <em>always<\/em> blo\u011funun bariz bir bi\u00e7imde 3 farkl\u0131 durumu <em>mux<\/em>&#8216;layan bir yap\u0131, ikinci <em>always<\/em> blo\u011funun ise basit bir kar\u015f\u0131la\u015ft\u0131rma \u0131\u015f\u0131\u011f\u0131nda <em>register<\/em> <em>setleme<\/em> veya <em>resetleme<\/em> oldu\u011funu g\u00f6rebiliyoruz.<\/p>\n<p><em><strong>#8: always bloklar\u0131 m\u00fcmk\u00fcn mertebe par\u00e7al\u0131 olmal\u0131d\u0131r<\/strong><\/em><br \/>\nMant\u0131k olarak bir \u00f6nceki \u00f6rnek ile ayn\u0131 \u00f6rnek. \u0130nceleyelim:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @(posedge in_clock) begin\n    if((sinyal1_r &lt; 503) &amp;&amp; (reg_in_control==1'b1))begin\n        cts_r &lt;= 1'b1; \n    end\n    else begin\n        cts_r &lt;= 1'b0;\n    end\n    if((sinyal2_r &lt; 503) &amp;&amp; (reg_in_control==1'b1))begin\n        rts_r &lt;= 1'b1; \n    end\n    else begin\n        rts_r &lt;= 1'b0;\n    end\nend \n...\n<\/pre>\n<p>Sanki biraz karma\u015f\u0131k bir kod gibi g\u00f6r\u00fcn\u00fcyor, halbuki \u00e7ok basit <em>register<\/em> <em>set\/reset<\/em> i\u015flemi. \u015eu \u015fekilde yaz\u0131l\u0131nca daha az tehditkar oluyor:<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\n...\nalways @(posedge in_clock) begin\n    if((sinyal1_r &lt; 503) &amp;&amp; (reg_in_control==1'b1))begin\n        cts_r &lt;= 1'b1; \n    end\n    else begin\n        cts_r &lt;= 1'b0;\n    end\nend\n\nalways @(posedge in_clock) begin\n    if((sinyal2_r &lt; 503) &amp;&amp; (reg_in_control==1'b1))begin\n        rts_r &lt;= 1'b1; \n    end\n    else begin\n        rts_r &lt;= 1'b0;\n    end\nend \n...\n<\/pre>\n<p>Umar\u0131m \u00f6neriler i\u015finize yarar, iyi tasar\u0131mlar.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>#5: Mod\u00fcllerde port isimlendirmeleri m\u00fcmk\u00fcnse standart olmal\u0131 ve m\u00fcmk\u00fcn mertebe a\u00e7\u0131klay\u0131c\u0131 olmal\u0131d\u0131r Kapsaml\u0131 bir say\u0131sal devre tasar\u0131m\u0131 yaparken giri\u015f\/\u00e7\u0131k\u0131\u015f kap\u0131lar\u0131 ile ilgili ya\u015fanan temel sorunlar ve zorluklar: Kap\u0131&#8230;<\/p>\n","protected":false},"author":1,"featured_media":361,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[207,191,209],"tags":[249,211,251,253,255,217,257,259],"class_list":["post-355","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-donanim-tr","category-teknik-tr","category-verilog-tr","tag-case-tr","tag-fpga-tr","tag-if-else-tr","tag-oneri-tr","tag-sayisal-tr","tag-verilog-tr","tag-vhdl-tr","tag-yazmac-tr"],"_links":{"self":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/355","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=355"}],"version-history":[{"count":1,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/355\/revisions"}],"predecessor-version":[{"id":1202,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/355\/revisions\/1202"}],"wp:featuredmedia":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/media\/361"}],"wp:attachment":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=355"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=355"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=355"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}