{"id":79,"date":"2013-10-15T13:25:04","date_gmt":"2013-10-15T10:25:04","guid":{"rendered":"http:\/\/www.scozturk.com\/?p=79"},"modified":"2025-08-27T10:17:14","modified_gmt":"2025-08-27T10:17:14","slug":"spartan-3e-starter-kit-nedir-nasil-kullanilir","status":"publish","type":"post","link":"http:\/\/18.193.70.38\/?p=79&lang=tr","title":{"rendered":"Spartan 3E Starter Kit nedir? Nas\u0131l kullan\u0131l\u0131r?"},"content":{"rendered":"<p><strong>1- Giri\u015f:<\/strong><\/p>\n<p>Spartan 3E Starter Kit Digilent firmas\u0131n\u0131n Xilinx Spartan 3E 500 modelli FPGAs\u0131 i\u00e7in \u00fcretti\u011fi bir geli\u015ftirme ortam\u0131d\u0131r. Bu ortam kullan\u0131larak FPGA denenebilir ve \u00e7e\u015fitli uygulamalar yap\u0131labilir.<\/p>\n<p>Bundan bir \u00f6nceki makalede ISE Webpack ile sentezleyip ger\u00e7ekledi\u011fimiz \u00f6rne\u011fi \u015fimdi Spartan 3E Starter Kit \u00fczerine y\u00fckleyece\u011fiz.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>2- iMPACT ile bit dosyas\u0131n\u0131n Spartan 3E Starter Kit\u2019e y\u00fcklenmesi:<\/strong><\/p>\n<p>\u00d6ncelikle bir \u00f6nceki yaz\u0131da ger\u00e7ekledi\u011fimiz verilog tasar\u0131m\u0131n\u0131n bulundu\u011fu projeyi a\u00e7al\u0131m. A\u015fa\u011f\u0131dakine benzer bir pencere kar\u015f\u0131m\u0131za \u00e7\u0131k\u0131yor:<\/p>\n<p><a title=\"verilog1.JPG\" href=\"http:\/\/web.archive.org\/web\/20100105172727\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog1.JPG\"><img decoding=\"async\" alt=\"verilog1.JPG\" src=\"http:\/\/web.archive.org\/web\/20100105172727im_\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog1.thumbnail.JPG\" \/><\/a><\/p>\n<p>\u015eimdi Spartan 3E Starter Kit\u2019imizin beslemesini a\u00e7al\u0131m ve bu sayede \u00e7al\u0131\u015ft\u0131ral\u0131m. A\u015fa\u011f\u0131daki resimde i\u015faretlenmi\u015f \u201c1\u2033 ile i\u015faretlenmi\u015f olan ba\u011flant\u0131 noktas\u0131 besleme, \u201c2\u2033 ile i\u015faretlenmi\u015f olan ba\u011flant\u0131 noktas\u0131 USB kap\u0131s\u0131 ( USB kablosunun bir ucu buraya di\u011fer ucu da bilgisayara tak\u0131lmal\u0131d\u0131r) ve \u201c3\u2033 ile i\u015faretlenmi\u015f olan kayan d\u00fc\u011fme ise Spartan 3E Starter Kit\u2019in \u00e7al\u0131\u015ft\u0131rma d\u00fc\u011fmesidir. USB ve g\u00fc\u00e7 ba\u011flant\u0131lar\u0131n\u0131 yapt\u0131ktan sonra kayan d\u00fc\u011fmeyi kayd\u0131rarak geli\u015ftirme kart\u0131m\u0131z\u0131 \u00e7al\u0131\u015ft\u0131rabiliriz.<br \/>\n<a title=\"verilog2.JPG\" href=\"http:\/\/web.archive.org\/web\/20100105172727\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog2.JPG\"><img decoding=\"async\" alt=\"verilog2.JPG\" src=\"http:\/\/web.archive.org\/web\/20100105172727im_\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog2.thumbnail.JPG\" \/><\/a><\/p>\n<p>Spartan 3E Starter Kit\u2019i bu \u015fekilde \u00e7al\u0131\u015ft\u0131rd\u0131\u011f\u0131m\u0131zda kit \u00fczerinde bulunan LCD\u2019nin ve LED\u2019lerin baz\u0131lar\u0131n\u0131n yand\u0131\u011f\u0131n\u0131 g\u00f6rece\u011fiz. Bunun nedeni geli\u015ftirme setinin a\u00e7\u0131l\u0131\u015fta \u00f6nceden tan\u0131ml\u0131 vhdl tasar\u0131m\u0131 FPGA\u2019ya y\u00fcklemesidir. A\u015fa\u011f\u0131daki \u015fekilde detayl\u0131 inceleme yapabilmek i\u00e7in baz\u0131 elemanlar i\u015faretlenmi\u015f ve numaraland\u0131r\u0131lm\u0131\u015ft\u0131r:<\/p>\n<p><a title=\"verilog3.JPG\" href=\"http:\/\/web.archive.org\/web\/20100105172727\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog3.JPG\"><img decoding=\"async\" alt=\"verilog3.JPG\" src=\"http:\/\/web.archive.org\/web\/20100105172727im_\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog3.thumbnail.JPG\" \/><\/a><\/p>\n<p>\u015eimdi numaral\u0131 elemanlar\u0131 tan\u0131tal\u0131m:<\/p>\n<p>1- Bu LED sayesinde FPGA kart\u0131na g\u00fc\u00e7 verilip verilmedi\u011fini anlayabilirsiniz.<\/p>\n<p>2- Bu LED sayesinde FPGA\u2019n\u0131n programlan\u0131p programlanmad\u0131\u011f\u0131n\u0131 anlayabilirsiniz.<\/p>\n<p>3- \u0130lklendirme d\u00fc\u011fmesi.<\/p>\n<p>4- Spartan 3E FPGA<\/p>\n<p>5- DDR SDRAM<\/p>\n<p>6- VGA Konnekt\u00f6r\u00fc<\/p>\n<p>7- PS2 Kap\u0131<\/p>\n<p>8- RS232 Kap\u0131s\u0131<\/p>\n<p>9- RS232 Kap\u0131s\u0131<\/p>\n<p>10- FX2 Konnekt\u00f6r\u00fc<\/p>\n<p>11- Ethernet Kap\u0131s\u0131<\/p>\n<p>12- D\u00f6rt y\u00f6nl\u00fc d\u00fc\u011fme<\/p>\n<p>13- LCD<\/p>\n<p>14- Kayan D\u00fc\u011fmeler<\/p>\n<p>Kart\u0131m\u0131z\u0131n \u00fczerindeki elemanlar\u0131 \u015f\u00f6yle bir tan\u0131d\u0131ktan kart\u0131m\u0131z\u0131 a\u00e7al\u0131m ve ard\u0131ndan verilog tasar\u0131m\u0131m\u0131za d\u00f6nelim ve soldaki men\u00fcden \u201cGenerate Programming File\u201d se\u00e7ene\u011fine \u00e7ift t\u0131klayal\u0131m. \u0130\u015flem tamamland\u0131ktan sonra \u201cGenerate Programming File\u201d se\u00e7ene\u011finin i\u00e7inde bulunan \u201cConfigure Device\u201d se\u00e7ene\u011fine \u00e7ift t\u0131klayal\u0131m. Bu i\u015flem biraz zaman alabilir. Herhangi bir\u015fey olmuyor gibi g\u00f6z\u00fckse de arka planda oluyor. Bir s\u00fcre sonra a\u015fa\u011f\u0131daki uyar\u0131 penceresi ile kar\u015f\u0131la\u015facaks\u0131n\u0131z:<\/p>\n<p><a title=\"verilog4.JPG\" href=\"http:\/\/web.archive.org\/web\/20100105172727\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog4.JPG\"><img decoding=\"async\" alt=\"verilog4.JPG\" src=\"http:\/\/web.archive.org\/web\/20100105172727im_\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog4.thumbnail.JPG\" \/><\/a><\/p>\n<p>\u201cOk\u201d diyerek bu mesaj\u0131 ge\u00e7menizin bir sak\u0131ncas\u0131 yok. \u015eimdi de a\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz:<\/p>\n<p><a title=\"verilog5.JPG\" href=\"http:\/\/web.archive.org\/web\/20100105172727\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog5.JPG\"><img decoding=\"async\" alt=\"verilog5.JPG\" src=\"http:\/\/web.archive.org\/web\/20100105172727im_\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog5.thumbnail.JPG\" \/><\/a><\/p>\n<p>Ekran g\u00f6r\u00fcnt\u00fcs\u00fcnde k\u0131rm\u0131z\u0131 ilei\u015faretlenmi\u015f birime sa\u011f t\u0131klay\u0131p kar\u015f\u0131m\u0131za \u00e7\u0131kan men\u00fcden \u201cProgram\u201d se\u00e7ene\u011fini se\u00e7elim. A\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz:<\/p>\n<p><a title=\"verilog6.JPG\" href=\"http:\/\/web.archive.org\/web\/20100105172727\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog6.JPG\"><img decoding=\"async\" alt=\"verilog6.JPG\" src=\"http:\/\/web.archive.org\/web\/20100105172727im_\/http:\/\/www.scozturk.com\/wp-content\/uploads\/2007\/07\/verilog6.thumbnail.JPG\" \/><\/a><\/p>\n<p>Bu pencerede herhangi bir se\u00e7ene\u011fi de\u011fi\u015ftirmeden \u201cOk\u201d d\u00fc\u011fmesine t\u0131klayarak tasar\u0131m\u0131m\u0131z\u0131 FPGA\u2019m\u0131za y\u00fckleyelim. Y\u00fckleme bitti\u011fi anda LEDlere bakacak olursak istedi\u011fimiz kara\u015fim\u015fek efektinin olu\u015ftu\u011funu g\u00f6rece\u011fiz.<\/p>\n<p><strong>3- Son:<\/strong><\/p>\n<p>Bu makalede Spartan 3E Starter Kit kullan\u0131m\u0131 g\u00f6rd\u00fck. Art\u0131k olu\u015fturdu\u011fumuz verilog tasar\u0131mlar\u0131n\u0131 geli\u015ftirme ortam\u0131m\u0131za y\u00fckleyip deneyebiliriz.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>1- Giri\u015f: Spartan 3E Starter Kit Digilent firmas\u0131n\u0131n Xilinx Spartan 3E 500 modelli FPGAs\u0131 i\u00e7in \u00fcretti\u011fi bir geli\u015ftirme ortam\u0131d\u0131r. Bu ortam kullan\u0131larak FPGA denenebilir ve \u00e7e\u015fitli uygulamalar yap\u0131labilir&#8230;.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[207,209],"tags":[],"class_list":["post-79","post","type-post","status-publish","format-standard","hentry","category-donanim-tr","category-verilog-tr"],"_links":{"self":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/79","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=79"}],"version-history":[{"count":1,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/79\/revisions"}],"predecessor-version":[{"id":1145,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/79\/revisions\/1145"}],"wp:attachment":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=79"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=79"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=79"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}