{"id":85,"date":"2013-10-15T13:27:01","date_gmt":"2013-10-15T10:27:01","guid":{"rendered":"http:\/\/www.scozturk.com\/?p=85"},"modified":"2025-08-27T10:17:00","modified_gmt":"2025-08-27T10:17:00","slug":"xilinx-ise-nedir-nasil-kullanilir","status":"publish","type":"post","link":"http:\/\/18.193.70.38\/?p=85&lang=tr","title":{"rendered":"Xilinx ISE nedir? Nas\u0131l kullan\u0131l\u0131r?"},"content":{"rendered":"

1- Xilinx ISE Webpack Nedir?<\/strong><\/em><\/p>\n

Xilinx ISE Webpack Xilinx firmas\u0131n\u0131n bedava da\u011f\u0131tt\u0131\u011f\u0131 ve Xilinx FPGAlar\u0131n\u0131n \u00fczerinde \u00e7al\u0131\u015f\u0131lmas\u0131n\u0131 sa\u011flayan bir yaz\u0131l\u0131md\u0131r. Verilog veya VHDL ile yaz\u0131lan kod sentezlenebilir ve Webpack arac\u0131l\u0131\u011f\u0131yla FPGA geli\u015ftirme ortam\u0131na y\u00fcklenebilir.<\/p>\n

Xilinx ISE Webpack yaz\u0131l\u0131m\u0131n\u0131 indirmek i\u00e7in http:\/\/www.xilinx.com\/ise\/logic_design_prod\/webpack.htm<\/a> adresine gitmeniz ve
\nkaydolman\u0131z gerekmektedir. Kay\u0131t olduktan sonra yaz\u0131l\u0131m\u0131 indirip bilgisayar\u0131n\u0131za
\nkurabilirsiniz.<\/p>\n

Yaz\u0131l\u0131m\u0131 bilgisayar\u0131n\u0131za kurduktan sonra gerekli ISE Webpack yaz\u0131l\u0131m g\u00fcncellemelerini yapmay\u0131 unutmay\u0131n\u0131z.<\/p>\n

2- Xilinx ISE Webpack Kullan\u0131m\u0131 – Sentez<\/em><\/strong><\/p>\n

Yaz\u0131l\u0131m\u0131n kullan\u0131m\u0131n\u0131 g\u00f6stermenin en iyi (ve kolay) y\u00f6ntemi bir \u00f6rnek olaca\u011f\u0131ndan bu b\u00f6l\u00fcmde Verilog dili ile bir kod yaz\u0131p sentezleyece\u011fiz. Yazd\u0131\u011f\u0131m\u0131z kod Spartan S3E Starter Kit \u00fczerindeki LED\u2019leri a\u00e7\u0131p kapamaya yarayacak.<\/p>\n

\n

\u00d6ncelikle bilgisayar\u0131m\u0131za kurdu\u011fumuz ISE Webpack yaz\u0131l\u0131m\u0131n\u0131 a\u00e7al\u0131m. A\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015faca\u011f\u0131z:<\/p>\n

\"s0_3_1.JPG\"<\/a><\/p>\n

Herhangi bir kod yazmadan \u00f6nce bir proje olu\u015fturmam\u0131z gerekmektedir. Bunu yapmak i\u00e7in pencerenin yukar\u0131s\u0131ndaki men\u00fcden File -> New Project<\/em> i se\u00e7elim. Se\u00e7ti\u011fimiz zaman a\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015faca\u011f\u0131z.<\/p>\n

\"s0_3_2.JPG\"<\/a><\/p>\n

Bu pencerede Project Name <\/em>kutucu\u011funa istedi\u011fimiz proje ad\u0131n\u0131 girelim. Ard\u0131ndan sa\u011fdaki Project Location <\/em>kutucu\u011funa da proje dosyalar\u0131m\u0131z\u0131 konumland\u0131raca\u011f\u0131m\u0131z klas\u00f6r\u00fc belirtelim. Top-Level Source Type<\/em> i\u00e7in ise HDL<\/em>\u2018i se\u00e7elim. \u015eimdi Next\u2019<\/em>e basabiliriz. A\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015faca\u011f\u0131z:<\/p>\n

\"s0_3_3.JPG\"<\/a> Bu pencerede kulland\u0131\u011f\u0131m\u0131z FPGA\u2019n\u0131n \u00f6zelliklerini se\u00e7ece\u011fiz. Product Category<\/em> olarak General Purpose <\/em>se\u00e7elim. Bu se\u00e7imi yapmam\u0131z\u0131n nedeni Xilinx firmas\u0131n\u0131n Spartan 3E<\/em>\u2018yi
\ngeneral purpose<\/em> kategorisine koymas\u0131d\u0131r. Ard\u0131ndan Family<\/em> olarak Spartan3E<\/em>\u2018yi se\u00e7elim. E\u011fer elinizde ba\u015fka bir FPGA var ise uygun olan FPGA\u2019y\u0131 listeden se\u00e7iniz. Ard\u0131ndan Device<\/em> kutucu\u011funa Spartan3E<\/em>\u2018nin hangi tipini kulland\u0131\u011f\u0131m\u0131z\u0131 yazmam\u0131z gerekiyor. S3E Starter Kit<\/em> \u00fczerinde bulunan S3E XC3S500E<\/em>\u2018dir. Bu y\u00fczden bu kutucuk i\u00e7in XC3S500E <\/em>se\u00e7imini yapal\u0131m. Package<\/em> kutucu\u011funa ise FG320<\/em> girelim. E\u011fer elinizdeki S3E Starter Kit<\/em> de\u011filse bu se\u00e7imi de farkl\u0131 yapman\u0131z gerekebilir. Speed<\/em> olarak ise -4<\/em> se\u00e7imini yapal\u0131m. Synthesis
\ntool<\/em> olarak Webpack<\/em> ile beraber gelen XST (VHDL\/Verilog) <\/em>se\u00e7imini yapal\u0131m. E\u011fer elinizde farkl\u0131 bir sentez program\u0131 var ise onu da kullanman\u0131z m\u00fcmk\u00fcn. Simulator olarak da yine Webpack<\/em> ile beraber gelen ISE Simulator (VHDL\/Verilog)<\/em>\u2018u se\u00e7elim. Preferred Language<\/em> olarak ise Verilog<\/em> se\u00e7elim. Di\u011fer ayarlar\u0131 da yukar\u0131daki resimdeki gibi yapt\u0131ktan sonra Next<\/em>\u2018e basal\u0131m. A\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz:<\/p>\n

\n

\"s0_3_4.JPG\"<\/a><\/p>\n

Bu pencere bizim proje dosyalar\u0131m\u0131z i\u00e7in
\nbir kaynak dosya olu\u015fturmam\u0131z\u0131 sa\u011fl\u0131yor. E\u011fer bir \u015fey de\u011fi\u015ftirmeden Next<\/em>
\nderseniz kaynak dosyalar\u0131n\u0131z\u0131 sonradan da olu\u015fturabilirsiniz. Biz burada \u00f6rnek
\nte\u015fkil etmesi a\u00e7\u0131s\u0131ndan yukar\u0131daki New Source\u2026<\/em> d\u00fc\u011fmesine basarak kaynak
\ndosyam\u0131z\u0131 olu\u015ftural\u0131m. A\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz:<\/p>\n

\"s0_3_5.JPG\"<\/a><\/p>\n

Soldaki listeden Verilog Module<\/em>\u2018\u00fc se\u00e7tikten sonra File Name<\/em> kutucu\u011funa dosyam\u0131z\u0131n ad\u0131n\u0131 girelim. Ard\u0131ndan da dosyam\u0131z\u0131n konumunu Location<\/em> kutucu\u011funa girelim (e\u011fer bir terslik yok ise zaten sizin i\u00e7in proje klas\u00f6r\u00fcn\u00fcz\u00fcn adresi bu kutucu\u011fa otomatik olarak yaz\u0131lacakt\u0131r). Bu penceredeki Next\u2019 et\u0131klayal\u0131m ve bir sonraki pencereye ge\u00e7elim:<\/p>\n

\"s0_3_6.JPG\"<\/a><\/p>\n

Bu pencere yard\u0131m\u0131yla tasar\u0131m\u0131m\u0131zdaki
\ni\u011fneleri belirtebiliyoruz. Bu a\u015famada bo\u015f b\u0131rak\u0131p ge\u00e7memizin herhangi bir
\nsak\u0131ncas\u0131 yok ama yine \u00f6rnek te\u015fkil etmesi i\u00e7in bu pencerede saat darbemizi ve
\nLED \u00e7\u0131k\u0131\u015f\u0131m\u0131z\u0131 belirtelim. \u0130lk olarak saat darbesi i\u011fnesini belirtelim. Bunun
\ni\u00e7in Port Name<\/em> kutucu\u011funa SAAT<\/em> yazal\u0131m. \u0130stedi\u011finiz ba\u015fka bir ad\u0131
\nda girebilirsizin. Direction<\/em> yani iletim y\u00f6n\u00fc i\u00e7in input<\/em> yani<\/p>\n

girdi<\/em>\u2018yi se\u00e7elim. Di\u011fer ayarlar\u0131 (Bus, MSB,LSB<\/em>) bo\u015f b\u0131rakabiliriz.
\nArd\u0131ndan kullanaca\u011f\u0131m\u0131z LED\u2019in i\u011fnesini belirtelim. Bunun i\u00e7in Port Name<\/em>\u2018e
\nLED yazal\u0131m ve Direction<\/em> olarak output<\/em> yani \u00e7\u0131kt\u0131<\/em>\u2018y\u0131
\nse\u00e7elim. Yine di\u011fer alanlar\u0131 bo\u015f b\u0131rakabiliriz. Yukar\u0131daki anlat\u0131lanlar\u0131
\nyapt\u0131\u011f\u0131m\u0131zda penceremiz a\u015fa\u011f\u0131daki hali al\u0131yor.<\/p>\n

\"s0_3_7.JPG\"<\/a><\/p>\n

\u015eimdi Next<\/em>\u2018e t\u0131klayarak di\u011fer
\npencereye ge\u00e7elim.<\/p>\n

\"s0_3_8.JPG\"<\/a><\/p>\n

Bu pencerede az \u00f6nce olu\u015fturdu\u011fumuz kaynak
\ndosyam\u0131z ve kap\u0131 bilgileri hakk\u0131nda bilgi veriliyor. Finish<\/em>\u2018e
\nbasabiliriz. Finish<\/em>\u2018e bast\u0131\u011f\u0131m\u0131zda e\u011fer proje klas\u00f6r\u00fcn\u00fcz ger\u00e7ekte yok ise
\nolmad\u0131\u011f\u0131na ama olu\u015fturulaca\u011f\u0131na dair bir uyar\u0131 alacaks\u0131n\u0131z. Aksi takdirde
\nherhangi bir uyar\u0131 almayacaks\u0131n\u0131z. A\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz:<\/p>\n

\"s0_3_9.JPG\"<\/a><\/p>\n

Olu\u015fturmu\u015f oldu\u011fumuz Verilog kayna\u011f\u0131n\u0131 listede g\u00f6rebiliyoruz. Bu \u00f6rnekte daha fazla mod\u00fcl olu\u015fturmak istemedi\u011fimizden<\/p>\n

Next<\/em>\u2018e basarak bir sonraki pencereye ge\u00e7elim.<\/p>\n

\"s0_3_10.JPG\"<\/a><\/p>\n

Yukar\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz.
\nE\u011fer \u00f6nceden olu\u015fturdu\u011funuz bir kaynak dosyas\u0131n\u0131 olu\u015fturmakta oldu\u011funuz projeye
\neklemek isterseniz bunu buradan yapabilirsiniz. Biz bu \u00f6rnekte bunu yapmayaca\u011f\u0131z
\nve Next\u2019e basaca\u011f\u0131z. Projenize yeni dosya ekleme ve var olan dosya ekleme
\ni\u015flemlerini sorunsuz olarak projenizi olu\u015fturduktan sonra da yapabilirsiniz,
\nunuttu\u011funuz herhangi bir \u015fey var ise panik yapmay\u0131n sonra da ekleyebilirsiniz.
\nNext\u2019e t\u0131klayal\u0131m.<\/p>\n

\"s0_3_11.JPG\"<\/a><\/p>\n

Yukar\u0131daki pencerede projemizin genel
\n\u00f6zellikleri hakk\u0131nda bilgilendiriliyoruz. E\u011fer \u00f6nceki a\u015famalarda yapt\u0131\u011f\u0131n\u0131z
\nayarlardan emin de\u011filseniz bu pencere yard\u0131m\u0131yla bunlar\u0131 kontrol edebilirsiniz.
\nFinish<\/em>\u2018e t\u0131klayal\u0131m. Ana penceremiz a\u015fa\u011f\u0131daki hali al\u0131yor:<\/p>\n

\"s0_3_12.JPG\"<\/a><\/p>\n

Yukar\u0131daki resimde 1 ile i\u015faretlenmi\u015f k\u0131s\u0131mda proje dosyalar\u0131n\u0131z\u0131 ve dosyalar\u0131n\u0131z aras\u0131ndaki ba\u011flant\u0131lar\u0131 g\u00f6rebilirsiniz. E\u011fer projenizin genel \u00f6zelliklerinde de\u011fi\u015fiklik yapman\u0131z gerekirse xc3s500e-4fg320<\/em> se\u00e7ene\u011fine sa\u011f t\u0131klay\u0131p Properties<\/em>\u2018i se\u00e7ip ayarlar\u0131n\u0131z\u0131 de\u011fi\u015ftirebilirsiniz.<\/p>\n

Resimde 2 ile i\u015faretlenmi\u015f b\u00f6l\u00fcmde ise 1\u2032de se\u00e7ti\u011finiz dosya \u00fczerinde yapabilece\u011finiz i\u015flemler listelenmektedir. Buraya biraz sonra d\u00f6nece\u011fiz.<\/p>\n

Resimde 3 ile i\u015faretlenmi\u015f k\u0131s\u0131m ise dosyan\u0131z\u0131 i\u00e7eri\u011finin g\u00f6r\u00fcnt\u00fclendi\u011fi yerdir. Dikkat edecek olursan\u0131z \u015fu an Design Summary<\/em> dosyas\u0131n\u0131 g\u00f6rmekteyiz. Bu Webpack ISE<\/em>\u2018\u0131n bize otomatik olarak olu\u015fturdu\u011fu bir penceredir. Bu pencerede tasar\u0131m\u0131m\u0131z hakk\u0131nda detayl\u0131
\nbilgi edinebilece\u011fiz. Buraya da az sonra geri d\u00f6nece\u011fiz.<\/p>\n

\u201cana.v\u201d dosyas\u0131n\u0131 se\u00e7elim. Penceremiz a\u015fa\u011f\u0131daki \u015fekli al\u0131yor.<\/p>\n

\"s0_3_13.JPG\"<\/a><\/p>\n

G\u00f6rd\u00fc\u011f\u00fcn\u00fcz gibi Webpack<\/em> otomatik
\nolarak girdi \u00e7\u0131kt\u0131 kap\u0131lar\u0131m\u0131z\u0131 ayarlam\u0131\u015f ve mod\u00fcl tan\u0131mlamam\u0131z\u0131 yapm\u0131\u015f. Bunun
\nnedeni projeyi olu\u015ftururken gerekli bilgileri girmemizdir. Girmeseydik bize bo\u015f
\nbir dosya verecekti. Yorum sat\u0131rlar\u0131n\u0131 silelim ve dosyay\u0131 kaydedelim. Ard\u0131ndan
\nsol \u00fcstteki k\u0131s\u0131mdan ana<\/em>\u2018y\u0131 se\u00e7elim. Sol alttaki k\u0131sm\u0131n otomatik olarak
\nde\u011fi\u015fti\u011fini g\u00f6rece\u011fiz:<\/p>\n

\"s0_3_14.JPG\"<\/a><\/p>\n

User Constraints, Synthesize – XST,
\nImlement Design, Generate Programming File<\/em> gibi se\u00e7eneklerin \u00e7\u0131kt\u0131\u011f\u0131n\u0131
\ng\u00f6r\u00fcyoruz. Kodumuzu sentezleyebilmek i\u00e7in Synthesize – XST<\/em>\u2018ye \u00e7ift
\nt\u0131klamam\u0131z yeterli olacakt\u0131r. Bu a\u015famada t\u0131klamam\u0131z\u0131n herhangi bir anlam\u0131 yok
\n\u00e7\u00fcnk\u00fc mod\u00fcl\u00fcm\u00fcz herhangi bir \u015fey yapm\u0131yor. Birka\u00e7 sat\u0131r kod yazmaya ge\u00e7elim.<\/p>\n

Bir tane yazma\u00e7 tan\u0131mlayal\u0131m. Bu yazmac\u0131 saya\u00e7 olarak kullanaca\u011f\u0131z. Kodumuz a\u015fa\u011f\u0131daki \u015fekli al\u0131yor:<\/p>\n

\n

\n
    \n
  1. <\/p><\/li>\n
  2. <\/li>\n
  3. <p\u00a0align=”justify”>\u00a0<code>`timescale\u00a01ns\u00a0\/\u00a01ps<\/code>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0module\u00a0ana(SAAT,\u00a0LED);<\/li>\n
  4. \/\/\u00a0girdi\u00a0kap\u0131lar\u0131<\/li>\n
  5. input\u00a0SAAT;<\/li>\n
  6. \/\/\u00a0\u00e7\u0131kt\u0131\u00a0kap\u0131lar\u0131<\/li>\n
  7. output\u00a0LED;\/\/\u00a0yazma\u00e7lar<\/li>\n
  8. reg\u00a0[25:0]\u00a0sayac;endmodule<\/li>\n
  9. <p\u00a0align=”justify”><\/li>\n<\/ol>\n<\/div>\n\n\n\n
    <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    G\u00f6rd\u00fc\u011f\u00fcn\u00fcz gibi sayac\u0131m\u0131z\u0131 26 bitlik
    \ntan\u0131mlad\u0131k. Bunu yapmam\u0131z\u0131n nedeni sayac\u0131m\u0131z\u0131n 50 000 000 say\u0131s\u0131na kadar
    \nsayd\u0131rmak istememizdir. Bunu yapmam\u0131z\u0131n nedeni ise saat darbemizin 50Mhz
    \nolmas\u0131d\u0131r. \u015eimdi de yazmac\u0131m\u0131z\u0131n ilk de\u011ferini belirtmek i\u00e7in initial<\/em>
    \nkomutunu kullanal\u0131m.<\/p>\n

    \n

    \n
      \n
    1. <\/p><\/li>\n
    2. <p\u00a0align=”justify”>\u00a0<\/p><\/li>\n
    3. <code>`timescale\u00a01ns\u00a0\/\u00a01ps<\/code>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0module\u00a0ana(SAAT,\u00a0LED);<\/li>\n
    4. \/\/\u00a0girdi\u00a0kap\u0131lar\u0131<\/li>\n
    5. input\u00a0SAAT;\/\/\u00a0\u00e7\u0131kt\u0131\u00a0kap\u0131lar\u0131<\/li>\n
    6. output\u00a0LED;<\/li>\n
    7. \/\/\u00a0yazma\u00e7lar<\/li>\n
    8. reg\u00a0[25:0]\u00a0sayac;\/\/\u00a0yazma\u00e7lara\u00a0ilk\u00a0de\u011ferler\u015f\u00a0vereliminitial\u00a0begin<\/li>\n
    9. sayac\u00a0<=\u00a026’b00000000000000000000000000;<\/li>\n
    10. end<\/li>\n
    11. <\/li>\n
    12. endmodule<\/li>\n
    13. <p\u00a0align=”justify”><\/li>\n<\/ol>\n<\/div>\n\n\n\n
      <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

      \u015eimdi de kodumuzun as\u0131l i\u015flevli k\u0131sm\u0131n\u0131
      \nkodlayal\u0131m. \u00d6ncelikle her pozitif saat darbesinde bir bir i\u015flem yap\u0131lmas\u0131
      \ngerekti\u011fini belirtmek i\u00e7in always<\/em> komutunu posedge <\/em>ile beraber
      \nkullanal\u0131m.<\/p>\n

      \n

      \n
        \n
      1. <\/p><\/li>\n
      2. <p\u00a0align=”justify”>\u00a0<\/p><\/li>\n
      3. <code>`timescale\u00a01ns\u00a0\/\u00a01ps<\/code>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0module\u00a0ana(SAAT,\u00a0LED);<\/li>\n
      4. \/\/\u00a0girdi\u00a0kap\u0131lar\u0131<\/li>\n
      5. input\u00a0SAAT;<\/li>\n
      6. \/\/\u00a0\u00e7\u0131kt\u0131\u00a0kap\u0131lar\u0131<\/li>\n
      7. output\u00a0LED;\/\/\u00a0yazma\u00e7lar<\/li>\n
      8. reg\u00a0[25:0]\u00a0sayac;\/\/\u00a0yazma\u00e7lara\u00a0ilk\u00a0de\u011ferler\u015f\u00a0verelim<\/li>\n
      9. initial\u00a0begin<\/li>\n
      10. sayac\u00a0<=\u00a026’b00000000000000000000000000;end\/\/\u00a0her\u00a0pozitif\u00a0saat\u00a0kenar\u0131nda\u00a0tetiklen<\/li>\n
      11. always\u00a0@\u00a0(posedge\u00a0SAAT)\u00a0begin<\/li>\n
      12. \/\/\u00a0Kodumuzu\u00a0buraya\u00a0yazaca\u011f\u0131z<\/li>\n
      13. end<\/li>\n
      14. <\/li>\n
      15. endmodule<\/li>\n
      16. <p\u00a0align=”justify”><\/li>\n<\/ol>\n<\/div>\n\n\n\n
        <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        \u015eimdi de always<\/em> blo\u011funun i\u00e7ine sayac\u0131m\u0131z\u0131 ve kar\u015f\u0131la\u015ft\u0131rmalar\u0131m\u0131z\u0131 kodlayal\u0131m.<\/p>\n\n\n\n
        `timescale 1ns \/ 1ps<\/code> module ana(SAAT, LED);
        \n\/\/ girdi kap\u0131lar\u0131
        \ninput SAAT;\/\/ \u00e7\u0131kt\u0131 kap\u0131lar\u0131
        \noutput LED;
        \n\/\/ yazma\u00e7lar
        \nreg [25:0] sayac;\/\/ yazma\u00e7lara ilk de\u011ferler\u015f vereliminitial begin
        \nsayac <= 26\u2032b00000000000000000000000000;
        \nend\/\/ her pozitif saat kenar\u0131nda tetiklen
        \nalways @ (posedge SAAT) beginif(sayac == 26\u2032b10111110101111000010000000) begin \/\/ 50M e ula\u015ft\u0131k m\u0131?
        \n\/\/ evet sayac\u0131 s\u0131f\u0131rla
        \nsayac <= 0;
        \n\/\/ kodumuzu buraya yazaca\u011f\u0131z
        \n\/\/
        \n\/\/end
        \nelse begin \/\/ 50M e ula\u015famad\u0131k o zaman artt\u0131rmaya devam
        \n\/\/ sayac de\u011ferini artt\u0131r
        \nsayac <= sayac + 1;
        \nend
        \nendendmodule<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Yukar\u0131daki kod ile sayac\u0131n 50000000
        \nde\u011ferine ula\u015f\u0131p ula\u015fmad\u0131\u011f\u0131n\u0131 kontrol ediyoruz ve uygun i\u015flemleri
        \nyapt\u0131r\u0131yoruz. \u015eimdi LED\u2019imizi a\u00e7\u0131p kapayacak kodu yazal\u0131m. LED \u00e7\u0131k\u0131\u015f
        \ni\u011fnesine direk olarak veri yazd\u0131ramad\u0131\u011f\u0131m\u0131zdan bir yazma\u00e7 daha tan\u0131mlayal\u0131m
        \nve bu yazmac\u0131 LED\u2019e ba\u011flayal\u0131m. Yazmac\u0131m\u0131z\u0131n ad\u0131 ledim<\/em> olsun. Her
        \n50000000\u2032da bir ledim<\/em> yazmac\u0131 terslensin. Di\u011fer saya\u00e7 de\u011ferlerinde
        \nde\u011feri sabit kals\u0131n.<\/p>\n\n\n\n
        `timescale 1ns \/ 1ps<\/code> module ana(SAAT, LED);
        \n\/\/ girdi kap\u0131lar\u0131
        \ninput SAAT;\/\/ \u00e7\u0131kt\u0131 kap\u0131lar\u0131
        \noutput LED;
        \n\/\/ yazma\u00e7lar
        \nreg [25:0] sayac;
        \nreg ledim;\/\/ yazma\u00e7lara ilk de\u011ferler\u015f verelim
        \ninitial begin
        \nsayac <= 26\u2032b00000000000000000000000000;
        \nend\/\/ her pozitif saat kenar\u0131nda tetiklenalways @ (posedge SAAT) begin
        \nif(sayac == 26\u2032b10111110101111000010000000) begin \/\/ 50M e ula\u015ft\u0131k m\u0131?
        \n\/\/ evet sayac\u0131 s\u0131f\u0131rla
        \nsayac <= 0;
        \n\/\/ ledim yazmac\u0131n\u0131 tersle
        \nledim <= ~ledim;end
        \nelse begin \/\/ 50M e ula\u015famad\u0131k o zaman artt\u0131rmaya devam
        \n\/\/ sayac de\u011ferini artt\u0131r
        \nsayac <= sayac + 1;
        \n\/\/ ledim yazmac\u0131 de\u011ferini korusun
        \nledim <= ledim;end
        \nendendmodule<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        \u015eimdi son olarak yapmam\u0131z gereken LED<\/em>
        \n\u00e7\u0131k\u0131\u015f\u0131na ledim<\/em> yazmac\u0131n\u0131 ba\u011flamak. Bunun i\u00e7in assign<\/em> komutunu
        \nkullanal\u0131m.<\/p>\n\n\n\n
        `timescale 1ns \/ 1ps<\/code> module ana(SAT, LED);
        \n\/\/ girdi kap\u0131lar\u0131
        \ninput SAAT;\/\/ \u00e7\u0131kt\u0131 kap\u0131lar\u0131
        \noutput LED;
        \n\/\/ yazma\u00e7lar
        \nreg [25:0] sayac;
        \nreg ledim;\/\/ yazma\u00e7lara ilk de\u011ferler\u015f verelim
        \ninitial begin
        \nsayac <= 26\u2032b00000000000000000000000000;
        \nend\/\/ her pozitif saat kenar\u0131nda tetiklenalways @ (posedge SAAT) begin
        \nif(sayac == 26\u2032b10111110101111000010000000) begin \/\/ 50M e ula\u015ft\u0131k m\u0131?
        \n\/\/ evet sayac\u0131 s\u0131f\u0131rla
        \nsayac <= 0;
        \n\/\/ ledim yazmac\u0131n\u0131 tersle
        \nledim <= ~ledim;end
        \nelse begin \/\/ 50M e ula\u015famad\u0131k o zaman artt\u0131rmaya devam
        \n\/\/ sayac de\u011ferini artt\u0131r
        \nsayac <= sayac + 1;
        \n\/\/ ledim yazmac\u0131 de\u011ferini korusun
        \nledim <= ledim;end
        \nend\/\/ LED \u00e7\u0131k\u0131\u015f\u0131na ledim yazmac\u0131n\u0131 ba\u011fla
        \nassign LED = ledim;endmodule<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Kodumuz \u015fu an haz\u0131r. Herhangi bir hata
        \nolup olmad\u0131\u011f\u0131n\u0131 kontrol edebilmek i\u00e7in kodumuzu sentezleyelim. Bunun i\u00e7in
        \nsoldaki listeden Synthesize<\/em>\u2018a \u00e7ift t\u0131klayal\u0131m (yada sa\u011f t\u0131klay\u0131p
        \nRun<\/em>\u2018\u0131 se\u00e7elim). A\u015fa\u011f\u0131daki resimde t\u0131klamam\u0131z gereken se\u00e7enek k\u0131rm\u0131z\u0131 ile
        \n\u00e7er\u00e7evelenmi\u015ftir.<\/p>\n

        \"s0_3_15.JPG\"<\/a><\/p>\n

        \u00c7ift t\u0131klad\u0131ktan sonra alttaki konsol penceresinden i\u015flem ak\u0131\u015f\u0131n\u0131 g\u00f6rebiliriz.<\/p>\n

        \"s0_3_16.JPG\"<\/a><\/p>\n

        Herhangi bir hata veya uyar\u0131 olu\u015fmad\u0131.
        \nAsl\u0131nda bir uyar\u0131 olu\u015ftu ama Webpack ISE ile alakal\u0131 olan \u00f6nemsiz bir uyar\u0131
        \noldu\u011fundan ald\u0131r\u0131\u015f etmesek de olur. \u015eimdi konsol \u00e7\u0131kt\u0131s\u0131n\u0131 biraz inceleyelim
        \n\u00e7\u00fcnk\u00fc istedi\u011fimiz sonucu al\u0131p almad\u0131\u011f\u0131m\u0131z hakk\u0131nda bilgi edinebilmek i\u00e7in bu
        \nverileri kullanabiliriz. Konsol \u00e7\u0131kt\u0131s\u0131n\u0131 par\u00e7a par\u00e7a inceleyelim.<\/p>\n\n\n\n
        Reading design: ana.prj<\/code>===========================* HDL Compilation *
        \n=======================================================Compiling verilog file \u201cana.v\u201d in library work
        \nModule <ana> compiledNo errors in compilation
        \nAnalysis of file <\u201dana.prj\u201d> succeeded.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Yukar\u0131daki k\u0131s\u0131mda hangi dosyalar\u0131n
        \nderlendi\u011fi ve derleme sonu\u00e7lar\u0131 hakk\u0131nda bilgi veriliyor. G\u00f6r\u00fcld\u00fc\u011f\u00fc gibi burada
        \nherhangi bir sorun yok. Bir sonraki b\u00f6l\u00fcme ge\u00e7elim:<\/p>\n\n\n\n

        \n=========================================================================
        \n* Design Hierarchy Analysis *
        \n=========================================================================
        \nAnalyzing hierarchy for module <ana> in library <work>.<\/code><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Bu k\u0131s\u0131mda proje i\u00e7indeki verilog
        \nmod\u00fclleri ile sentezlenen mod\u00fcl aras\u0131ndaki ba\u011flant\u0131lar inceleniyor. Tek kaynak
        \ndosyam\u0131z ve tek mod\u00fcl\u00fcm\u00fcz oldu\u011fundan burada herhangi bir \u015fey g\u00f6remiyoruz.<\/p>\n\n\n\n

        \n==================================<\/code> * HDL Analysis *==========================
        \nAnalyzing top module <ana>.
        \nModule <ana> is correct for synthesis.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Bu k\u0131s\u0131mda ise mod\u00fcl\u00fcm\u00fcz\u00fcn
        \nsentezlenebilir olup olmad\u0131\u011f\u0131 kontrol ediliyor. Unutmay\u0131n verilog ile
        \nyaz\u0131lan her kod sentezlenebilir de\u011fildir ve bu da bazen sorunlar
        \nyaratabilir. Zaten kod sentezlenebilir de\u011filse Webpack kodu
        \nsentezleyemeyecektir ve bundan haberiniz olacakt\u0131r. Buna dikkat etmemiz
        \ngerekiyor.<\/p>\n\n\n\n

        \n====================================================================<\/code> * HDL Synthesis *
        \n===================================================Performing bidirectional port resolution\u2026Synthesizing Unit <ana>.Related source file is \u201cana.v\u201d.
        \nFound 1-bit register for signal <ledim>.
        \nFound 26-bit up counter for signal <sayac>.
        \nSummary:inferred 1 Counter(s).
        \ninferred 1 D-type flip-flop(s).
        \nUnit <ana> synthesized.=====================================================HDL Synthesis ReportMacro Statistics
        \n# Counters : 1
        \n26-bit up counter : 1
        \n# Registers : 11-bit register : 1=====================================================<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Bu k\u0131s\u0131mda HDL sentezi yap\u0131l\u0131yor.
        \nMod\u00fcl\u00fcm\u00fcz hakk\u0131ndaki bilgileri burada g\u00f6rebiliriz. Mesela 1 bitlik ledim<\/em>
        \nyazmac\u0131, 26 bitlik sayac<\/em> yazmac\u0131, sayac\u0131m\u0131z ve d tipi flip flobumuzun
        \noldu\u011fu buradan anla\u015f\u0131labiliyor. Konsol \u00e7\u0131kt\u0131s\u0131n\u0131 incelemeyi bitirdi\u011fimizde
        \nsentezlenmi\u015f mod\u00fcl\u00fcm\u00fcz\u00fcn \u015femas\u0131na bakaca\u011f\u0131z. Bir sonraki k\u0131sma bakal\u0131m:<\/p>\n\n\n\n

        \n=========================================================================
        \n* Advanced HDL Synthesis *
        \n=========================================================================<\/code> Loading device for application Rf_Device from file \u20183s500e.nph\u2019 in
        \nenvironment C:\\Xilinx91i.=======================================================Advanced HDL Synthesis ReportMacro Statistics
        \n# Counters : 126-bit up counter : 1
        \n# Registers : 1
        \nFlip-Flops : 1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Burada ise daha detayl\u0131 bir sentez
        \nraporu yer al\u0131yor. Mod\u00fcl\u00fcm\u00fcz m\u00fcmk\u00fcn olabilecek en basit mod\u00fcllerden biri
        \noldu\u011fu i\u00e7in herhangi bir fark g\u00f6rmememiz normal.<\/p>\n\n\n\n

        \n=========================================================================
        \n* Low Level Synthesis *
        \n=========================================================================<\/code> Optimizing unit <ana> \u2026Mapping all equations\u2026
        \nBuilding and optimizing final netlist \u2026
        \nFound area constraint ratio of 100 (+ 5) on block ana, actual ratio is
        \n0.Final Macro Processing \u2026=====================================================Final Register ReportMacro Statistics# Registers : 27
        \nFlip-Flops : 27=====================================================<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Bu k\u0131s\u0131mda ise alt seviye sentez
        \nhakk\u0131nda bilgiler yer al\u0131yor. Eniyileme i\u015flemi ve benzeri i\u015flemler hakk\u0131nda
        \nbilgiyi buradan edinebiliriz.<\/p>\n\n\n\n

        \n=========================================================================
        \n* Partition Report *
        \n=========================================================================<\/code> Partition Implementation Status
        \n\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014-No Partitions were found in this design.\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014-<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Yukar\u0131daki k\u0131s\u0131mda b\u00f6l\u00fcmlendirme raporu
        \nbulunuyor. Herhangi bir b\u00f6l\u00fcmlendirme kullanmad\u0131\u011f\u0131m\u0131zdan burada da herhangi
        \nbir \u015fey g\u00f6remiyoruz. Zaten raporda da herhangi bir b\u00f6l\u00fcmlendirme
        \nbulunamad\u0131\u011f\u0131na dair bir ibare yer al\u0131yor.<\/p>\n\n\n\n

        \n=========================================================================<\/code> * Final Report *
        \n=======================================================Clock Information:
        \n\u2014\u2014\u2014\u2014\u2014\u2014
        \n\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2013+\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014+\u2014\u2014-+Clock Signal | Clock buffer(FF name) | Load |
        \n\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2013+\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014+\u2014\u2014-+
        \nSAAT | BUFGP | 27 |
        \n\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2013+\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014+\u2014\u2014-+Asynchronous Control Signals Information:\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014-
        \nNo asynchronous control signals found in this designTiming Summary:
        \n\u2014\u2014\u2014\u2014\u2014
        \nSpeed Grade: -4Minimum period: 5.179ns (Maximum Frequency: 193.101MHz)
        \nMinimum input arrival time before clock: No path found
        \nMaximum output required time after clock: 4.310ns
        \nMaximum combinational path delay: No path found=======================================================WARNING:ProjectMgmt – \u201cD:\/scozturk_projeler\/s0_3\/proje_1\/ana.ngr\u201d line 0
        \nduplicate design unit: \u2018Module|ana\u2019Process \u201cSynthesize\u201d completed successfully<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Bu k\u0131s\u0131mda ise son rapor var. Burada saat darbesi hakk\u0131nda bilgiler veriliyor ve FPGA\u2019n\u0131n \u00e7al\u0131\u015fabilece\u011fi frekanslar belirtiliyor. Burada dikkat edilmesi gereken bir detaydan
        \nbahsedeyim. Diyelim ki mod\u00fcl\u00fcn\u00fczde bir saat darbesi kullan\u0131yorsunuz. E\u011fer
        \nsaat darbeniz yukar\u0131da listelenmemi\u015fse (dikkat ederseniz SAAT i\u011fnemizin
        \nlistelenmi\u015f oldu\u011funu g\u00f6r\u00fcrs\u00fcn\u00fcz) mod\u00fcl\u00fcn\u00fczde bir sorun vard\u0131r. Webpack b\u00f6yle
        \nbir durumda hata veya uyar\u0131 vermeyebilir ama her \u015feye ra\u011fmen kodunuzda bir
        \nhata veya terslik olabilir ve bu durum kodunuzun d\u00fczg\u00fcn \u00e7al\u0131\u015fmamas\u0131na neden
        \nolabilir. B\u00f6yle bir durum ile kar\u015f\u0131la\u015f\u0131rsan\u0131z kodunuzu tekrar kontrol edin.
        \nYaz\u0131l\u0131ma \u00e7ok fazla g\u00fcvenmeyin.<\/p>\n

        \u015eimdi Synthesize<\/em>\u2018\u0131n solundaki + i\u015faretine t\u0131klayal\u0131m ve View RTL Schematic<\/em>\u2018e \u00e7ift t\u0131klayal\u0131m. A\u00e7\u0131lan pencerede mod\u00fcl\u00fcm\u00fcz\u00fcn olu\u015fturulmu\u015f \u015femas\u0131n\u0131 g\u00f6rebiliriz:<\/p>\n

        \"s0_3_17.JPG\"<\/a><\/p>\n

        SAAT giri\u015fini ve LED \u00e7\u0131k\u0131\u015f\u0131n\u0131 g\u00f6rebiliyoruz. Daha detayl\u0131 olarak \u015femam\u0131z\u0131 g\u00f6rebilmek i\u00e7in \u015feman\u0131n \u00fczerine \u00e7ift t\u0131klayal\u0131m.<\/p>\n

        \"s0_3_18.JPG\"<\/a><\/p>\n

        Yukar\u0131daki resimde devre elemanlar\u0131m\u0131z\u0131 daha rahat bir \u015fekilde g\u00f6rebiliyoruz. E\u011fer sentezledi\u011finiz mod\u00fcl\u00fcn\u00fcz i\u00e7in bir \u015fema olu\u015fturulmuyorsa kodunuzda hata var demektir. Webpack<\/em> bu konuda da sizi uyarmayabilir. Bu y\u00fczden sentezledikten sonra RTL<\/em> \u015feman\u0131z\u0131 kontrol ediniz. \u015eemaya dikkat edecek olursak sayac\u0131m\u0131z\u0131, kar\u015f\u0131la\u015ft\u0131r\u0131c\u0131m\u0131z\u0131 ve flip
        \nflopumuzu g\u00f6rebiliyoruz. Burada baz\u0131 elemanlar\u0131n \u00fczerine \u00e7ift t\u0131klayarak bu
        \nelemanlar hakk\u0131nda daha detayl\u0131 bilgi elde etmemiz m\u00fcmk\u00fcn olabilir. Mesela bu
        \nmod\u00fcl i\u00e7in kar\u015f\u0131la\u015ft\u0131r\u0131c\u0131m\u0131za \u00e7ift t\u0131klarsak i\u00e7eri\u011fini g\u00f6rebiliriz.<\/p>\n

        \u015eemay\u0131 kapatabiliriz.<\/p>\n

        3- Xilinx ISE Webpack Kullan\u0131m\u0131 – Ger\u00e7ekle\u015ftirim<\/em><\/strong><\/p>\n

        Bu b\u00f6l\u00fcmde sentezlemi\u015f oldu\u011fumuz mod\u00fcl\u00fc
        \nger\u00e7ekle\u015ftirece\u011fiz. Mod\u00fcl\u00fcm\u00fcz\u00fc ger\u00e7ekle\u015ftirebilmek i\u00e7in soldaki se\u00e7eneklerden<\/p>\n

        Implement Design<\/em> se\u00e7ene\u011fine \u00e7ift t\u0131klayal\u0131m (yada sa\u011f t\u0131klay\u0131p Run<\/em>\u2018\u0131
        \nse\u00e7elim).<\/p>\n

        \"s0_3_19.JPG\"<\/a><\/p>\n

        \u0130\u015flem bitti\u011finde konsoldan i\u015flemin bitti\u011fine dair bir mesaj alaca\u011f\u0131z. Tabii ki \u015fimdi bir sorunumuz var. Biz fiziksel olarak FPGA\u2019n\u0131n hangi i\u011fnelerine LED ve SAAT i\u011fnelerini atad\u0131\u011f\u0131m\u0131z\u0131 belirtmedik. Bunu belirtmek i\u00e7in UCF<\/em> dosyas\u0131n\u0131 doldurmam\u0131z gerekiyor.
        \nUCF<\/em> dosyas\u0131n\u0131 doldurmak i\u00e7in soldaki se\u00e7eneklerden User Constraints<\/em>\u2018in
        \nsolundaki + i\u015faretine t\u0131klayal\u0131m ve Edit Constraints (Text)<\/em>\u2018e \u00e7ift
        \nt\u0131klayal\u0131m. Webpack size UCF dosyas\u0131n\u0131n olu\u015fturulup projeye eklenmesini isteyip
        \nistemedi\u011fini soracak (e\u011fer \u00f6nceden eklemediyseniz). Evet dedikten sonra
        \na\u015fa\u011f\u0131daki pencere ile kar\u015f\u0131la\u015f\u0131yoruz:<\/p>\n

        \"s0_3_20.JPG\"<\/a><\/p>\n

        \u015eimdi Spartan S3E Starter Kit <\/em>kullan\u0131m k\u0131lavuzundan saat darbesi i\u00e7in ve LED i\u00e7in UCF bilgilerine bakal\u0131m. Clock Sources<\/em> ba\u015fl\u0131\u011f\u0131n\u0131n alt\u0131ndaki UCF Constraints<\/em> alt ba\u015fl\u0131\u011f\u0131na
        \ngelelim:<\/p>\n

        \"s0_3_21.JPG\"<\/a><\/p>\n

        Burada saat darbeleri ile alakal\u0131
        \na\u015fa\u011f\u0131daki UCF<\/em> bilgilerini g\u00f6r\u00fcyoruz:<\/p>\n\n\n\n

        \nNET \"CLK_50MHZ\" LOC = \"C9\" | IOSTANDARD = LVCMOS33 ;<\/code>
        \nNET \u201cCLK_SMA\u201d LOC = \u201cA10\u2033 | IOSTANDARD = LVCMOS33 ;
        \nNET \u201cCLK_AUX\u201d LOC = \u201cB8\u2033 | IOSTANDARD = LVCMOS33 ;
        \nNET \u201cCLK_50MHZ\u201d PERIOD = 20.0ns HIGH 40%;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Biz sadece 50Mhz\u2019lik saat
        \ndarbesini kullanmak istedi\u011fimizden sadece 50Mhz\u2019lik UCF <\/em>bilgilerini
        \nal\u0131p UCF<\/em> dosyam\u0131za yazal\u0131m. Yazarken CLK_50MHZ<\/em> etiketini<\/p>\n

        SAAT<\/em> etiketiyle de\u011fi\u015ftirmeyi unutmay\u0131n\u0131z.<\/p>\n

        Bunun ard\u0131ndan yine kullan\u0131m k\u0131lavuzundan
        \nSwitches, Button and Knob<\/em> ba\u015fl\u0131\u011f\u0131ndan Discrete LEDs<\/em> alt ba\u015fl\u0131\u011f\u0131n\u0131
        \nse\u00e7elim ve buradan UCF Location Constraints<\/em> alt ba\u015fl\u0131\u011f\u0131na ge\u00e7elim.<\/p>\n

        \"s0_3_22.JPG\"<\/a><\/p>\n

        Biz yukar\u0131daki sekiz LED \u00e7\u0131k\u0131\u015f\u0131ndan sadece tekini kullanaca\u011f\u0131z. Bu y\u00fczden LOC=\u201dF9\u2033<\/em> (F9 i\u011fnesindeki) LED \u00e7\u0131k\u0131\u015f bilgisini UCF<\/em> dosyam\u0131za yazal\u0131m. LED<7><\/em> olarak girilmi\u015f olan
        \netiketi LED<\/em> olarak de\u011fi\u015ftirmeyi unutmay\u0131n\u0131z.<\/p>\n

        UCF dosyam\u0131z \u00fczerinde de\u011fi\u015fiklikleri tamamlay\u0131nca dosyam\u0131z\u0131 kaydetti\u011fimizden emin olal\u0131m. UCF dosyam\u0131z\u0131n son \u015fekli a\u015fa\u011f\u0131dad\u0131r:<\/p>\n

        \"s0_3_23.JPG\"<\/a><\/p>\n

        Yukar\u0131daki resimde k\u0131rm\u0131z\u0131 ile i\u015faretlenmi\u015f yerde bir soru i\u015faretinin olu\u015ftu\u011funu g\u00f6receksiniz. Bunun nedeni UCF dosyas\u0131 olu\u015fturup bunu kaydetmi\u015f olmam\u0131zd\u0131r. Ger\u00e7ekle\u015ftirme i\u015fleminde bir UCF dosyas\u0131 var ise UCF dosyas\u0131ndaki bilgileri kullanarak sentezlenmi\u015f kod ger\u00e7ekle\u015ftirilir, yok ise rastgele i\u011fneler kullan\u0131l\u0131r. Yani bu a\u015famada yapmam\u0131z gereken \u015fey kodumuzu yeniden ger\u00e7ekle\u015ftirmektir.<\/p>\n

        E\u011fer herhangi bir hata yap\u0131lmam\u0131\u015f ise ger\u00e7ekle\u015ftirme i\u015flemi ba\u015far\u0131 ile sonu\u00e7lanacakt\u0131r. Tabii ki yukar\u0131daki resimdeki UCF dosyas\u0131na dikkat ederseniz etiket olarak LED yazmam gerekirken yanl\u0131\u015fl\u0131kla LCD yazm\u0131\u015f\u0131m. Bu y\u00fczden konsoldan a\u015fa\u011f\u0131daki hatalar\u0131 ald\u0131m:<\/p>\n\n\n\n
        <\/code> ERROR:NgdBuild:755 – \u201cana.ucf\u201d Line 4: Could not find net(s) \u2018LCD\u2019 in
        \nthe
        \nERROR:Parsers:11 – Encountered unrecognized constraint while parsing.
        \nERROR:NgdBuild:19 – Errors found while parsing constraint file \u201cana.ucf\u201d.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        UCF dosyas\u0131nda gerekli d\u00fczeltmeyi yapt\u0131ktan sonra yeniden ger\u00e7ekle\u015ftirme yaparsak herhangi bir sorun kalmayacakt\u0131r. UCF dosyam\u0131z\u0131n ger\u00e7ek son \u015fekli a\u015fa\u011f\u0131dad\u0131r:<\/p>\n

        \"s0_3_24.JPG\"<\/a><\/p>\n

        Kodumuz ba\u015far\u0131 ile ger\u00e7eklendi. Bundan bir sonraki a\u015fama Bitstream<\/em> dosyas\u0131n\u0131n Generate Programming File<\/em>\u2018a \u00e7ift t\u0131klanarak olu\u015fturulmas\u0131 ve FPGA geli\u015ftirme kart\u0131na y\u00fcklenmesidir. Tabii ki bundan \u00f6nce Spartan S3E Starter Kit\u2019<\/em>i biraz tan\u0131mam\u0131z gerekiyor.<\/p>\n

        Bu makalede yapacaklar\u0131m\u0131z bu kadar. ISE Webpack<\/em> kullan\u0131m\u0131n\u0131 en basit \u015fekliyle g\u00f6rm\u00fc\u015f olduk. Webpack <\/em>kullanarak devremizin sim\u00fclasyonunu yapmak ve Spartan S3E Starter Kit<\/em>\u2018e verileri g\u00f6ndermek hakk\u0131nda bilgi i\u00e7in l\u00fctfen sonraki makaleleri inceleyiniz.<\/p>\n

        4- Proje Dosyalar\u0131 (ISE)<\/em><\/strong><\/p>\n

        \u0130ndirmek i\u00e7in buraya t\u0131klay\u0131n\u0131z.<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

        1- Xilinx ISE Webpack Nedir? Xilinx ISE Webpack Xilinx firmas\u0131n\u0131n bedava da\u011f\u0131tt\u0131\u011f\u0131 ve Xilinx FPGAlar\u0131n\u0131n \u00fczerinde \u00e7al\u0131\u015f\u0131lmas\u0131n\u0131 sa\u011flayan bir yaz\u0131l\u0131md\u0131r. Verilog veya VHDL ile yaz\u0131lan kod sentezlenebilir ve…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[207,209],"tags":[],"class_list":["post-85","post","type-post","status-publish","format-standard","hentry","category-donanim-tr","category-verilog-tr"],"_links":{"self":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/85","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=85"}],"version-history":[{"count":1,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/85\/revisions"}],"predecessor-version":[{"id":1142,"href":"http:\/\/18.193.70.38\/index.php?rest_route=\/wp\/v2\/posts\/85\/revisions\/1142"}],"wp:attachment":[{"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=85"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=85"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/18.193.70.38\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=85"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}